Hardware Intership #1

Title : FPGA Development Intern – IP10 CoDec Implementation

Target : Electronics engineer

In-house competence centers : FPGA / Video / Compression

Job description :

We are looking for a motivated and technically skilled intern to join our development team. The intern will work closely with our engineers to design and implement an IP10 CoDec (coder-decoder) system on an FPGA. This is an excellent opportunity for students or recent graduates to gain hands-on experience in FPGA development, digital signal processing, and communication systems.

The following points will be addressed :

• Implement the IP10 CoDec algorithm on an FPGA platform.
• Collaborate with the team to optimize the design for performance, power, and resource utilization.
• Conduct simulations and testing of the IP10 CoDec implementation to ensure functionality and compliance with project specifications.
• Analyze and debug hardware design issues, providing solutions and enhancements.
• Contribute to the documentation of the design, testing procedures, and results.
• Present progress updates and technical challenges to the team.

Hardware Intership #2

Title : FPGA Development Intern – AXI4-MM FIFO with CDC

Target : Electronics engineer

In-house competence centers : FPGA / SoC

Job description :

The intern will work closely with our engineers to design and implement a new IP Core (for internal use) that combines FIFO and clock domain switching functionality for an AXI4-MM bus. This is an excellent opportunity for students or recent graduates to gain hands-on experience in FPGA development and in the development of an IP Core intended to be used in the context of a standard bus.

The following points will be addressed :

• Implement the IP Core on an FPGA platform.
• Collaborate with the team to optimize the design for performance, power, and resource utilization.
• Conduct simulations and testing of the IP Core implementation to ensure functionality and compliance with project specifications.
• Analyze and debug hardware design issues, providing solutions and enhancements.
• Contribute to the documentation of the design, testing procedures, and results.
• Present progress updates and technical challenges to the team.

Hardware Intership/TFE #3

Title : Aurora Protocol on Microchip FPGAs

Target : Electronics engineer

In-house competence centers : FPGA 

Job description :

The work consists of developing and validating an FPGA IP core designed to implement the Aurora protocol (64b/66b version) on a Microchip PolarFire FPGA. This protocol, invented by Xilinx (now AMD), is a very lightweight communication protocol that enables point-to-point data transfer over one or more high-speed serial lanes (typically several Gbps). Aurora 64B/66B is a more recent version of the protocol, using 64B/66B encoding instead of 8B/10B.

The following points will be addressed :

• Specification and modeling of the Aurora protocol (point-to-point, full-duplex).
• RTL coding (in VHDL) of the IP core (with multi-lane support – up to 4).
• Use of the PolarFire hardware 64b/66b encoders/decoders.
• Integration with PolarFire transceivers.
• Timing constraint management using Libero SoC.
• Functional verification through simulation (with ModelSim or Questa).
• Deployment on an evaluation board with real-time verification and link analysis (logic analyzer, ILA debug or equivalent).
• Setup of a test environment in loopback and in communication with an external Aurora link implemented on a Xilinx/AMD device (interoperability testing).

Hardware Intership/TFE  #4

Title : DMA Controller no DDR 

Target : Electronics engineer

In-house competence centers : FPGA 

Job description :

As part of the development of a new architecture, the objective of the work is to design and implement a custom PCI Express (PCIe) DMA controller on FPGA. This controller must perform on-the-fly data transfers between the FPGA and a host system, using a scatter-gather mechanism to efficiently handle non-contiguous memory buffers.

In its current version, Deltatec’s PCI Express DMA controller relies on storing the data to be transmitted, as well as the descriptors used for scatter-gather, in the DDR local memory attached to the FPGA.

The main challenge of the work is to minimize memory usage on the FPGA side and avoid using the FPGA’s attached DDR local memory, while still guaranteeing throughput, latency, and robustness of the DMA engine.

The designer will be involved in the entire development chain: architecture, RTL implementation, integration, board-level validation, and performance measurement.

The following points will be addressed :

• Analyze the existing solution and the constraints of the target system (PCIe bandwidth, FPGA resources, latency, protocols).
• Design the architecture of a new optimized scatter-gather DMA.
• Implement the controller in RTL (VHDL).
• Develop the mechanisms for scatter-gather descriptor management and on-the-fly processing.
• Integrate the controller into the FPGA environment.
• Develop testbench tools and validation scenarios (simulation + board testing).
• Measure and analyze performance (throughput, occupancy, memory usage).
• Write the technical documentation and propose future improvement paths.

Hardware Intership/TFE #5

Title : Real-time HDR keyer implementation on FPGA for the broadcast market

Target : Electronics engineer

In-house competence centers : FPGA 

Job description :

As part of the development of professional video solutions for the broadcast sector, the work involves designing and implementing a real-time HDR (High Dynamic Range) keyer on FPGA. 
The goal is to enable video compositing (chroma key or luma key) within an HDR stream, ensuring impeccable image quality, low latency, and compliance with modern broadcast standards (PQ, HLG, BT.2020, etc.).
The designer will participate in defining the architecture, implementing the video processing blocks, managing color spaces, and optimizing the pipeline for FPGA execution. 

The following points will be addressed :

• Analyze HDR broadcast specifications (formats, color spaces, dynamic ranges).
• Define the video pipeline architecture for a real-time HDR keyer (conversion, keying, blending, filtering).
• Design HDR keying algorithms :
  • Key extraction in a suitable HDR color space,
  • HDR blending respecting dynamic range and metadata.
• Implement the processing blocks in VHDL.
• Optimize latency, numerical precision, and FPGA resource usage.
• Integrate the complete chain into the FPGA environment (video interfaces).
• Develop simulation tools, testbenches, and board-level tests.
• Evaluate performance: visual quality, latency, throughput, logic utilization.
• Produce technical documentation and propose future improvements.

If you are interested in one or more of our internship/TFE topics, please do not hesitate to request a full description of the work or other information using the form below (mentioning the topic number).